verilog-flow-skill

Category: Tools & Productivity | Uploader: bjwanneng | Downloads: 0 | Version: v1.0（Latest）

Industrial-grade Verilog design pipeline with script-controlled orchestration and LLM-executed stages. Use when working with Verilog/RTL design, FPGA/ASIC development, hardware verification, or when you mention Verilog code generation, testbench generation, or hardware design workflows.

Changelog: Source: GitHub https://github.com/bjwanneng/Veriflow

Directory Structure

Current level: Root

📁 prompts/
- 📄 stage0_init.md 2.9 KB
- 📄 stage1_spec.md 14.6 KB
- 📄 stage2_timing.md 27.5 KB
- 📄 stage3_codegen.md 13.5 KB
- 📄 stage4_sim.md 10.3 KB
- 📄 stage5_synth.md 2.9 KB
- 📄 stage6_close.md 1.4 KB
📁 verilog_flow/
- 📁 common/
  - 📄 __init__.py 859 B
  - 📄 experience_db.py 7.4 KB
  - 📄 kpi.py 4.5 KB
- 📁 defaults/
  - 📁 coding_style/
    
    📁 generic/
    
    📄 base_style.md 20.0 KB
    
    📄 timing_patterns.md 6.5 KB
    
    📁 intel/
    
    📄 intel_style.md 4.7 KB
    
    📁 xilinx/
    
    📄 xilinx_style.md 4.7 KB
  - 📁 templates/
    
    📁 generic/
    
    📄 template_async_fifo.v 5.3 KB
    
    📄 template_axi4_lite_slave.v 7.0 KB
    
    📄 template_axis_skid_buffer.v 7.7 KB
    
    📄 template_cdc_handshake.v 3.8 KB
    
    📄 template_cdc_sync_bit.v 1.9 KB
    
    📄 template_fsm.v 5.1 KB
    
    📄 template_module_empty.v 3.7 KB
    
    📄 template_ram_sp.v 4.5 KB
    
    📄 template_ram_tdp.v 3.9 KB
    
    📄 template_rom.v 2.3 KB
    
    📄 template_sync_fifo.v 4.1 KB
- 📁 stage1/
  - 📁 schemas/
    
    📄 arch_spec_v2.json 7.7 KB
📄 .gitignore 70 B
📄 README.md 9.9 KB
📄 README_EN.md 10.1 KB
📄 readme_first.md 3.9 KB
📄 request.md 8.5 KB
📄 SKILL.md 4.6 KB
📄 veriflow_ctl.py 75.0 KB

SKILL.md

---
name: verilog-flow-skill
description: Industrial-grade Verilog design pipeline with script-controlled orchestration and LLM-executed stages. Use when working with Verilog/RTL design, FPGA/ASIC development, hardware verification, or when you mention Verilog code generation, testbench generation, or hardware design workflows.
license: MIT
metadata:
  author: VeriFlow Team
  version: "8.1.0"
  category: hardware-design
---

# VeriFlow-Agent 8.1 — Gate-Controlled Pipeline

Architecture: **Script as gatekeeper, LLM as executor.**
- `veriflow_ctl.py` enforces stage ordering, prerequisites, and validation gates
- You (Claude Code) drive the flow and execute each stage's creative tasks
- You cannot skip stages or mark incomplete work as done — the script prevents it

## Pipeline Stages

| Stage | Name | Key Output |
|-------|------|------------|
| 0 | Project Initialization | Directory structure, project_config.json |
| 1 | Micro-Architecture Spec | `stage_1_spec/specs/*_spec.json` |
| 2 | Virtual Timing Modeling | YAML scenarios, golden traces, Cocotb tests |
| 3 | RTL Code Generation + Lint | `stage_3_codegen/rtl/*.v`, testbenches |
| 4 | Simulation & Verification | Testbenches, sim logs (all PASS) |
| 5 | Synthesis Analysis | Yosys synthesis, synth_report.json |
| 6 | Closing | `reports/final_report.md` |

## EXECUTION PROTOCOL

**You MUST follow this exact loop. Do NOT deviate.**

The controller script path is relative to this skill's directory:
```
CTL="<SKILL_DIR>/veriflow_ctl.py"
```
Where `<SKILL_DIR>` is the directory containing this SKILL.md file. Resolve it to an absolute path before use. For example, if this skill is installed at `~/.claude/skills/verilog-flow-skill/`, then:
```bash
CTL="$HOME/.claude/skills/verilog-flow-skill/veriflow_ctl.py"
```

### Loop: repeat until all stages complete

**Step 1 — Get next stage prompt**
```bash
python "$CTL" next -d "PROJECT_DIR"
```
- If output starts with `BLOCKED:` → a prerequisite stage is incomplete. Fix it first.
- If output starts with `ALL_STAGES_COMPLETE` → pipeline is done. Stop.
- Otherwise, the output contains `---BEGIN_PROMPT---` ... `---END_PROMPT---` with the full task instructions.

**Step 2 — Execute the tasks**
Read the prompt output from Step 1 and execute ALL tasks described in it. This is where you do the real work: generate specs, write Verilog, create testbenches, run simulations, etc.

**Step 3 — Validate**
```bash
python "$CTL" validate -d "PROJECT_DIR" STAGE_NUMBER
```
- If `VALIDATION_PASSED` → proceed to Step 4.
- If `VALIDATION_FAILED` → read the errors, fix them, then re-run validate. Do NOT proceed until validation passes.

**Step 4 — Mark complete**
```bash
python "$CTL" complete -d "PROJECT_DIR" STAGE_NUMBER
```
- If `STAGE_COMPLETE` → go back to Step 1 for the next stage.
- If `REFUSED` → validation failed internally. Fix errors and retry.

**Step 5 — (If needed) Ask user before proceeding to next stage**
Check `.veriflow/project_config.json` `confirm_after_validate`. If true (or field missing), use AskUserQuestion to confirm with the user before moving to the next stage. Show them a brief summary of what was accomplished.

### Rollback (when stuck)
If a stage repeatedly fails and the root cause is in an earlier stage:
```bash
python "$CTL" rollback -d "PROJECT_DIR" TARGET_STAGE
```
This clears all completion markers after TARGET_STAGE. Then resume the loop from Step 1.

### Check progress anytime
```bash
python "$CTL" status -d "PROJECT_DIR"
```

## IMPORTANT RULES

1. **Always use the controller** — never manually create `.veriflow/stage_completed/` marker files
2. **Never skip validation** — always run `validate` before `complete`
3. **Fix errors in-place** — if validation fails, fix the files and re-validate; do not move on
4. **One stage at a time** — the controller enforces sequential execution
5. **requirement.md** — the project directory must contain a `requirement.md` file describing the design
6. **EDA toolchain PATH** — the controller auto-detects tool paths across platforms. If tools are not found, add them manually:
   - Windows: `export PATH="/c/oss-cad-suite/bin:/c/oss-cad-suite/lib:$PATH"`
   - macOS: `export PATH="/opt/homebrew/bin:$PATH"`
   - Linux: `export PATH="/opt/oss-cad-suite/bin:$PATH"`
7. **Cross-platform shell commands** — avoid `| tee`, `| head`, `timeout` (not available on all platforms). Use file redirection (`> file.log 2>&1`) instead. Testbench watchdog timers handle simulation timeouts.
8. **Coding style from project config** — always read `.veriflow/project_config.json` `coding_style` for reset type/signal, naming conventions, etc. Do not hardcode `rst_n` or assume async active-low reset.

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